Modern consumer electronics, such as cellular phones, digital cameras, and music players, are packing more integrated circuits into an ever-shrinking physical space with expectations for decreasing cost. Numerous technologies have been developed to meet these requirements. Some of the research and development strategies focus on new technologies while others focus on improving the existing and mature technologies. Research and development in the existing technologies may take a myriad of different directions.
Consumer electronics requirements demand more integrated circuits in an integrated circuit package while paradoxically providing less physical space in the system for the increased integrated circuits content. Continuous cost reduction is another requirement. Some technologies primarily focus on integrating more functions into each integrated circuit. Other technologies focus on stacking these integrated circuits into a single package. While these approaches provide more functions within an integrated circuit, they do not fully address the requirements for lower height, smaller space, and cost reduction.
One proven way to reduce cost is to use mature package technologies with existing manufacturing methods and equipments. Paradoxically, the reuse of existing manufacturing processes does not typically result in the reduction of package dimensions. Still the demand continues for lower cost, smaller size and more functionality. Continued integration of functions into a single integrated circuit increases the integrated circuit size necessitating a more expensive package or a higher profile package.
To further condense the packaging of individual devices, packages have been developed in which more than one device can be packaged on a package site of a lead frame strip. Each package site on a lead frame strip is a structure that provides mechanical support for the individual IC dice. It also provides one or more layers of interconnect lines that enable the devices to be connected electrically to surrounding circuitry. Various board-on-chip (“BOC”) techniques are used to attach different semiconductor die to a printed circuit board (“PCB”). BOC techniques include flip chip attachment, wire bonding, and tape automated bonding (“TAB”).
In some cases, multi-chip devices can be fabricated faster and more cheaply than a corresponding single IC chip that incorporates all the same functions. Current multi-chip modules typically consist of a PCB substrate onto which a set of separate IC chip components is directly attached. Such multi-chip modules have been found to increase circuit density and miniaturization, improve signal propagation speed, reduce overall device size and weight, improve performance, and lower costs, all of which are primary goals of the computer industry.
However, such multi-chip modules can be bulky. The area required to mount a die or module on a circuit board determines the IC package density. One method for reducing the board size of multi-chip modules and thereby increase their effective density is to stack the die or chips vertically within the module or package. In one design, a pair of IC die is mounted on opposite sides of a lead frame paddle. Gold or aluminum wires then connect the wire bonding pads on both the upper die and the lower die with the ends of their respective lead frame lead extensions.
Higher integration can be achieved through chip scale package (CSP) applications such as flip chip technology. Flip chip technology can employ area arrays for bump pads including connections to a carrier, thereby reducing package area and shortening transmission paths. A flip chip is generally a semiconductor device, such as an integrated circuit, having bead-like terminals formed on one surface of the chip. The terminals serve to both secure the chip to a circuit board and electrically connect the flip chip's circuitry to a conductor pattern formed on the circuit board, which may be a ceramic substrate, printed wiring board, flexible circuit, a substrate, or a lead frame. The typical flip chip is generally quite small, resulting in the terminals being crowded along the perimeter. As a result, conductor patterns are typically composed of numerous conductors often spaced closely.
Flip chip offers increased I/O density but may not be the best interconnect option for other integrated circuit devices. For example, integrated circuits providing a large number of functions may benefit from the flip chip interface. Other devices may have dense and repetitive functions, such as memory devices, that do not require a flip chip interface and may be more cost effective using wire bonding.
To meet this demand, the integrated circuit packages, such as quad flat nonleaded (QFN) package, are becoming popular owing to its small form factor, good thermal and electrical performance. A combination of the QFN package and flip chip technology would provide an attractive package. However, one problem in the conventional assembly of a flip chip on QFN lead frame is the challenge of integrating various other types of integrated circuits with different interfaces into a single package.
Thus, a need still remains for an integrated circuit package system providing low cost manufacturing, improved yield, improved reliability, and low profile. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.